Technical Field
The present disclosure relates to integrated circuits, and more particularly, to contact lines having insulating spacers therein, and a method of forming the same.
Related Art
Transistors, e.g., field-effect-transistors (FETs), generally include source, drain, and gate terminals. The gate terminal controls current between the source and drain terminals. Transistors may be formed over a substrate and may be disposed within a dielectric layer, e.g., inter-level dielectric layer. Contacts may be formed to each of the source, drain, and gate terminals through the dielectric layer in order to provide electrical connection between the transistor and other semiconductor devices that may be formed subsequent to the transistor in other metal levels. The contacts to the source and drain terminals of the FET are typically formed in an opening that extends through a dielectric layer.
Contacts may be formed to include a liner layer, such as a refractory metal layer, barrier layer, or nucleation layer, which substantially lines or coats the opening. Additionally, a conductive metal may be formed over the liner layer to substantially fill the opening. Further, a planarization technique may be employed to remove any material outside of the opening to form contact lines.
Depending on the application for the integrated circuit, it may be desirable to provide an insulating spacer within contact lines to electrically isolate one portion of a contact line from another. However, as integrated circuits continue to be scaled down, the real estate on the integrated circuit becomes more valuable in order to maintain the performance characteristics comparable to that of larger integrated circuits.